Microcomputers are sophisticated, general purpose logic devices which can be programmed to perform a wide variety of useful functions in various devices such as communication equipment, medical devices, and other apparatus such as educational devices, household appliances, consumer goods, and the like. Generally, an entire spectrum of microcomputers is available in the marketplace. In particular medical devices, such as implantable devices, e.g., implantable pacemakers and defibrillators, data processors should have maximum processing capability. However, such maximum processing capability must be weighed against the need for low power requirements. For example, such low power processor designs are available from Motorola under the 6811 C trade designation, from Intel under the 8052 trade designation, etc.
The architecture of a data processor pertains to the various component parts of the processor and interconnection therebetween. A data processor typically uses a central processing unit (CPU) as the controller for the other component parts. The CPU is generally interfaced to or includes an arithmetic logic unit (ALU).
The ALU is a device which accepts data and performs certain operations thereon. These operations are generally grouped as either arithmetic or logical in nature. The CPU controls the data delivered to and selects the operation of the ALU which performs an operation on the actual bit structure of the data so as to implement the desired functions. The data is stored within the CPU or alternatively in other accessible memory in the form of data words. The length of the data word is used to describe the data processor since the length is directly related to the precision of the data processor. A 16-bit data word processor has the capability of defining the number with much more precision than a 4-bit data word processor.
The data processor accepts data, manipulates it using the ALU, and places it in an inactive state such as retained in a memory until the data is later needed. Communication channels electrically connect the CPU with memory. The CPU responds to instructions stored as machine language. Machine language is instructions coded into a word, generally, of the same length as the data word. The instructions are stored in the memory and are retrieved by the CPU.
Since the memory contains both data and instructions for the data processor, some flag or signal is used to keep the processor from confusing what it is receiving from the memory. For example, an architecture may provide for flagging of the data and instructions stored in memory. Such an arrangement allows the data processor to perform tasks according to prioritization. When a high priority task interrupts a lower priority task, then the lower priority task operation is halted and the data in the processor and the status information relating to the lower task is stored in a memory until the higher priority task is completed. Once completed, the process is set at the state where the lower priority task was interrupted.
The throughput of any given data processor is a function of, among other things, the number of machine cycles required to execute a given set of instructions. In the course of designing any computer system, and in particular a microcomputer, a set of instructions is selected which will provide the anticipated requirements for the projected market in which the computer system is to be used, e.g., a low power processing unit for medical devices. Generally, the processor executes each instruction as a sequence of machine cycles, with the more complex instructions consuming a greater number of machine cycles. The operation of internal registers and gating circuitry of the data processor is synchronized by a master clock signal applied to the data processor. During a basic clock cycle, also commonly known as the machine cycle, a number of internal processor related operations may take place simultaneously, including the transfer of digital information from a bus to a register or vice-versa between certain registers, from an address or data buffer to a bus or vice-versa and so forth, the individual conductors of a bus may each be set to the predetermined logic level, or the contents of a register may be set to a predetermined logic level. The more processor operations occurring within an individual machine cycle, the fewer the number of machine cycles required for the execution of a particular instruction.
Various techniques have been used for implementing multiply and/or divide functions in data processors. For example, conventional microprocessors have implemented multiply and divide operations using microcode or using firmware. However, implementation of such operations in conventional manners has resulted in less than adequate processing capabilities, particularly for low power data processors. For example, with regard to microcode (i.e., an internal program which executes external instructions provided by the user), the microcode is generally stored in an internal memory array. Generally, program counter logic receives an external instruction and then accesses a microcode entry or jumps to a microcode routine to execute the external instruction, e.g., a multiply or divide instruction. The program counter logic may include mechanisms for waits, conditional jumps, and sequencing of instructions stored in the microcode (also known as microinstructions). The data processor stores data in internal registers and moves data internally using data paths.
When the program counter logic accesses the microcode, it provides a data element known as a microinstruction, which includes fields defining hardware of the processor to be enabled, data to be moved, etc. The fields are encoded, and a decoder is necessary to convert the field into control signals which enable and disable the hardware for operation. When the user provides an external arithmetic instruction, e.g., a multiply or a divide instruction, the microcode causes data to be moved via the internal data paths to the arithmetic hardware and activates appropriate portions of the hardware to perform the external instruction.
For example, when the microcode provides a multiply microinstruction, fields in the microinstruction cause the operands to move via the internal data paths and to be provided as inputs to a hardware multiplier. Conventional hardware multipliers, such as booth multipliers and array multipliers, are known to provide high speed operation and are frequently used in processor design. However, such high speed multipliers operate with unacceptably long delays for servicing interrupts for the data processor. Further, such multipliers also consume a lot of power and thus present limitations to the operation of data processors which are required to operate in low power environments, e.g., implantable devices. In addition, a significant amount of hardware is required to implement the algorithm resulting in increased die size. In other words, in a low power processor which generally operates at a low clock rate, it is unacceptable to have an instruction like a multiply or divide which executes for many sequential clock cycles without permitting interruption. Such is the case with a microcode/hardware implementation of a multiply and/or divide operation.
With regard to a firmware implementation of a multiplication or division, such a delay problem in servicing interrupts is not problematic. The firmware implementation can be interrupted at virtually any point in the multiplication or division operation. However, in conventional firmware implementations of a multiply or a divide operation, generally either a large number of instructions are required for performing such a multiply or divide operation or a smaller number of instructions are needed which loop over and over but which causes the CPU to spend more time managing the loop, rather than performing the multiply/divide function. For example, in one case 64 instructions are necessary to perform a multiply or divide operation on a 16-bit processor, and 96 instructions are generally required for such an operation on an 8-bit processor. Such a large number of instructions are undesirable. The number of instructions or loops should be minimized so as to minimize the number of machine cycles utilized during a particular multiplication or division operation. With reduction in the number of such machine cycles, device longevity is increased and lower power consumption is achieved.
Further, in low power processor designs, especially for use in implantable devices, chip size reduction is also of importance. Generally, any reduction in chip space used is desirable.
Various implementations of multiply and divide functions are known in the art, some examples of which may be found in the issued U.S. Patents listed in Table 1 below.
TABLE 1 U.S. Pat. No. Inventor(s) Issue Date 5,241,492 Girardeau, Jr. 31 August 1993 4,337,519 Nishimoto 29 June 1982 4,238,833 Ghest, et al. 9 December 1980 4,665,500 Poland 12 May 1987
All patents listed in Table 1 hereinabove are hereby incorporated by reference herein in their respective entireties. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, the Detailed Description of the Embodiments, and the claims set forth below, many of the devices and methods disclosed in the patents of Table 1 may be modified advantageously by using the teachings of the present invention.